Electronic packages composed of multiple laminated integrated circuit chips, or layers containing integrated circuitry, offer significantly decreased volume and improved signal propagation speed. A metallization pattern is often provided directly on one (or more) side face of such a multichip package for integrated circuit interconnections and for electrical connection of integrated circuits to circuitry external to the module. The stack metallization pattern can include both individual contacts and bussed contacts. A multichip module comprising a stack of integrated circuit chips is referred to herein as a "multichip stack."
Recently, a multichip stack has been presented having electrical connect on an end face thereof, see commonly assigned U.S. Pat. No. 5,426,566, entitled "Multichip Integrated Circuit Packages and Systems," which is hereby incorporated herein by reference. This document describes side face and end face metallizations which allow multiple stacks of integrated circuit chips to be directly electrically interconnected. One feature of the structures disclosed is the use of active integrated circuit chips at one or both ends of the multichip stacks. Traditionally, the end chips in a multichip stack comprise ceramic or "dummy" chips provided to facilitate the creation of conventional "T-connects" over wire outs to one or more side face of the stack from the penultimate chips.
Disclosed in the designated patent document is the use of a relatively thick layer of dielectric material, such as polyimide, over active integrated circuit chips disposed at the ends of the multichip stack. This dielectric layer, which has a thickness less than that of a conventional ceramic chip, includes a metal patterned to electrically couple metal on the end face of the stack to metal on a selected side face(s) of the stack. Electrical connection at the side face is attained via a special modified "T-connect," which comprises a modified pad deposited on the side face to electrically connect to an exposed wire out.
Notwithstanding the viability of the above-summarized structure, presented herein is an alternative technique to producing a practical endcap for a multichip stack having a minimized thickness. As briefly noted, the most common endcap technology employed with multichip stacks today consists of a multi-layer ceramic substrate with thick-film internal wiring, typically tungsten. In order to minimize thermal expansion problems with a silicon-based multichip stack, an AlN ceramic is used. Unfortunately, there are several limitations inherent in this technology.
Because AlN ceramic is relatively brittle, the ceramic endcap can only be thinned to approximately 375 micrometers (.mu.m). Increased thinning can result in unacceptably high yield loss due to cracking and breakage. However, for many applications, especially plastic encapsulated stacks, stack height is critical, with a strong need to make the total multichip stack as thin as possible. Therefore, limiting the thickness of an endcap chip to 375 .mu.m can be an undesirable restriction. Further, a ceramic endcap requires the use of thick-film wiring ground rules, which are much larger than the thin-film wiring ground rules employed with semiconductor devices. Thus, the use of a ceramic endcap with thick film wiring unnecessarily limits the wiring density achievable on the endcap chip, and therefore, the input/output (I/O) density of the entire multichip stack.
Additionally, the use of dissimilar metals, for example, tungsten for the endcap wiring and a titanium/aluminum or titanium/aluminum-copper alloy for stack side face wiring, can create severe problems where the two metals electrically and physically interface. In addition to the problems associated with interconnection of two dissimilar metals, there can be restrictions on processing environment and chemical exposure resulting from the use of two different metals. For example, an acceptable process chemical exposure for one metal might be unacceptable for the other metal.
Another problem area relates to the formation of the ceramic endcaps. Currently, a ceramic endcap is diced from a larger laminate using mechanical dicing techniques. Unfortunately, mechanical dicing techniques result in endcap size variations, with typical tolerances being +/-5 .mu.m. Such size variation often means increased stack side face polishing to expose transfer metallurgy leads, which adds cost to the stack fabrication process. Further, in order to minimize ceramic endcap edge defects, which can create significant problems when attempting to process the side face(s) of a stack, the dicing rate of the laminate is significantly reduced. Currently, ceramic endcaps might be diced at 1/10th the standard dicing rate. Such a restriction severely limits manufacturing throughput, and increases inspection requirements and time of manufacture, which ultimately increases stack fabrication costs.
This disclosure is directed towards solutions to the above-noted drawbacks and restrictions of existing stack fabrication technology and significantly improves upon the state of the multichip packaging art.